Parasitic Inductance in High-Frequency SiC Converters

In silicon IGBT converters switching at 5-20 kHz, parasitic inductance is a nuisance. In SiC converters switching at 50-200 kHz with dI/dt rates exceeding 5 A/ns, it becomes a primary design constraint. The same 10 nH of busbar inductance that produces a 50V spike at 5 A/ns produces a 500V spike at 50 A/ns - potentially exceeding device voltage ratings on a 800V bus with no remaining margin. This article covers the physics of parasitic inductance in high-frequency power conversion, the sources that matter most, and the design techniques that keep voltage stress within bounds without sacrificing the switching speed advantage that motivated the SiC selection in the first place.

1. Why Inductance Matters More at High Frequency

Parasitic inductance is present in every converter regardless of technology. The voltage it generates is V = L x dI/dt. At 10 kHz with a silicon IGBT turning off 200A in 500 ns, dI/dt is 0.4 A/ns and 10 nH produces 4V - trivial against a 600V bus. The same 10 nH in a SiC converter turning off 200A in 40 ns generates 50V, and at 10 A/ns it generates 100V. On a 800V bus with a 1200V device, 100V of additional overshoot consumes half the available margin. At 25 A/ns it fills the margin entirely.

The relationship is linear but the consequence is not - there is no averaging or statistical mitigation. Every switching event at maximum current produces the full overshoot voltage, and it appears superimposed on the bus voltage at the device terminals. A converter that passes static voltage withstand testing can fail in switching service when the combination of bus voltage, overshoot, and ringing exceeds device ratings.

The second effect of inductance in high-frequency converters is LC resonance. The parasitic inductance of the commutation loop resonates with the output capacitance (Coss) of the devices, producing ringing at the switching node. This ringing adds to peak voltage stress, generates radiated EMI across a broad frequency range, and can couple back into control and gate driver circuits.

2. Sources of Parasitic Inductance

The total commutation loop inductance is the sum of all inductive elements in the path that current follows during a switching event: from the DC bus capacitor, through the upper device, through the load, back through the lower device, and back to the capacitor. Each physical segment contributes.

The total commutation loop inductance for a discrete-device PCB design is typically 20 to 60 nH without careful layout. With a laminated busbar and optimized PCB, 5 to 15 nH is achievable. Purpose-built SiC power modules target 5 to 10 nH. Direct-die designs with integrated busbars can achieve 2 to 5 nH.

3. Voltage Overshoot Calculation

During turn-off, the current through the commutation loop decreases at dI/dt determined by the gate drive speed. The energy stored in the parasitic inductance cannot transfer instantaneously to the bus capacitor, so it appears as a voltage spike across the device:

Vpeak = Vbus + L_loop x dI/dt + Vring

Where Vring is the additional peak voltage from LC resonance after the initial spike. For a first-order estimate:

Vpeak,ring = Vbus + (L_loop / Coss)^0.5 x Ipeak

For L_loop = 15 nH, Coss = 200 pF (typical 1200V SiC MOSFET at Vbus), and Ipeak = 150A: the characteristic impedance is 274 ohms and the ringing voltage amplitude is 41V. Combined with a 50V spike from dI/dt = 10 A/ns, total peak voltage is 800 + 50 + 41 = 891V against a 1200V rating. This leaves 309V margin - acceptable but not generous.

If the designer reduces gate resistance to speed up turn-off and dI/dt increases to 20 A/ns, the spike doubles and the margin reduces to 209V. At the device's maximum junction temperature, Coss changes, Vth shifts, and the margin may erode further. Overshoot calculations must be validated with measurement at worst-case operating conditions, not only at room temperature and partial load.

4. Device Package Inductance

The choice of device package directly determines a floor on achievable loop inductance. Traditional TO-247 packages contribute 10-20 nH of internal inductance from the lead frame and bond wires. The four-pin TO-247 variant (TO-247-4L, used by Wolfspeed and others for SiC) separates the Kelvin source from the power source, reducing the inductance in the gate loop but not the power loop.

Chip-scale and surface-mount packages (TO-263, D2PAK, SMD) reduce package inductance to 2-5 nH but introduce thermal resistance challenges. Power modules eliminate lead inductance within the package but replace it with internal busbar inductance, which varies significantly by module design - from 5 nH in optimized SiC modules to 20+ nH in legacy module designs adapted for SiC.

Direct-die approaches, where the SiC chips are bonded directly to the power substrate without an intermediate module package, can reduce package inductance below 2 nH. This represents the lowest achievable floor and is the architecture preferred for the highest switching frequency applications.

5. Power Loop and Busbar Inductance

The inductance of the current path external to the device package is determined by the geometry of the conductors forming the commutation loop. Inductance scales approximately with the area enclosed by the loop and inversely with conductor width. For a single rectangular conductor of length l and width w at height h above a ground plane:

L ≈ 2l x ln(2h/w) nH (with dimensions in cm)

The critical insight is that two conductors carrying current in opposite directions with close proximity cancel their magnetic fields, dramatically reducing net inductance. This is the principle behind laminated busbars.

6. Laminated Busbar Design

A laminated busbar consists of positive and negative DC bus conductors separated by a thin insulating layer, bonded under pressure. Current flows in opposite directions on the two conductors, and their magnetic fields cancel to a degree determined by conductor separation - the closer the conductors, the stronger the cancellation and the lower the net inductance.

Insulating materials for laminated busbars at 800-1500V DC include Kapton (polyimide) film, Nomex, FR4, and Mylar. Kapton provides high dielectric strength (up to 100 kV/mm) with low thermal expansion mismatch, making it the preferred choice for high-frequency designs. A 0.1 mm Kapton layer can withstand over 7 kV, providing substantial margin at 1200V bus voltages.

Key design parameters for laminated busbars in SiC applications:

• Conductor thickness: 2 to 5 mm copper, balanced between current carrying capacity and skin-depth losses at high frequency. At 100 kHz, skin depth in copper is approximately 0.21 mm, so conductors thicker than 0.5 mm carry current only in the outer skin layers.
• Conductor width: Maximize within mechanical constraints. Each doubling of width roughly halves inductance for a fixed length.
• Interleaving: For three-phase or multi-phase designs, interleaving positive and negative bars of all phases within the same laminated structure further reduces inductance through additional field cancellation.
• Termination method: Bolted connections at device terminals should minimize loop area. Flexible copper braid transitions from rigid busbar to device terminals accommodate thermal expansion without introducing long flexible leads.

7. PCB Power Loop Layout

For designs using discrete SiC devices on PCB, the power loop is formed by the traces connecting the DC link capacitors to the device drain and source pads. Minimizing this loop area is the single most impactful layout action available to the PCB designer.

In a half-bridge configuration, the optimal layout places the high-side and low-side devices close together, with DC link capacitors immediately adjacent. The positive and negative bus connections to the capacitors should be on adjacent copper layers, routed directly beneath the switching node to maximize flux cancellation. A 4-layer PCB with dedicated inner power planes outperforms a 2-layer design by a factor of 3-5 in power loop inductance for the same footprint.

• Device placement: High-side drain pad directly connected to positive bus; low-side source pad directly connected to negative bus. Switching node (mid-point) connects internally between devices - minimize this connection length.
• Capacitor placement: DC link capacitors within 10 mm of device pads. Each additional centimeter of trace adds approximately 1-2 nH.
• Via stitching: Multiple vias in parallel between layers reduce via inductance. A single 0.5 mm via contributes approximately 1 nH; eight vias in parallel reduce this to 0.13 nH.
• Copper pour fill: Fill unused PCB area with copper connected to the appropriate bus potential, reducing the inductance of traces that run over the fill.

8. Decoupling Capacitor Selection and Placement

DC link capacitors serve a dual function: they supply switching current during transients (reducing the inductance the device switching current must traverse), and they absorb the energy released from parasitic inductance during turn-off. Their equivalent series inductance (ESL) is as important as their capacitance value for high-frequency operation.

The optimal decoupling strategy uses two stages: a low-ESL film capacitor (or paralleled array) as the main DC link, and small ceramic capacitors placed as close as physically possible to the device switching node for high-frequency bypassing. The ceramic capacitors supply current during the first few nanoseconds of the switching event before the film capacitor can respond through its own ESL and the remaining connection inductance.

9. Kelvin Source and Gate Loop Inductance

The gate loop inductance is separate from the power loop inductance but interacts with it. The power source terminal carries switching current; if the gate driver return is connected to this terminal rather than a dedicated Kelvin source, the dI/dt-induced voltage in the power source inductance appears in series with the gate drive signal. At 5 A/ns and 3 nH of source inductance, this is 15V - comparable to the gate drive voltage and capable of dramatically altering switching waveforms.

The consequence of inadequate Kelvin source routing is not always obvious. The switching waveform may look approximately correct on a probe connected to the power source terminal, but the actual gate voltage is distorted. Switching losses measured by probing Vds and Id may appear normal while the actual device junction is experiencing a different waveform. This is a systematic measurement error that can mask a genuine design problem until the device accumulates stress under field conditions.

Gate loop inductance targets: below 5 nH is achievable with careful layout; below 2 nH requires dedicated attention to gate trace routing, Kelvin pin connection, and bypass capacitor placement.

10. Snubber Design

When parasitic inductance cannot be reduced below the level required to keep voltage overshoot within device ratings, a snubber circuit absorbs the excess energy. The two practical options for SiC converters are RC snubbers and RCD snubbers.

An RC snubber placed across the device (drain to source) provides a low-impedance path for high-frequency ringing energy. The resistor damps the LC resonance; the capacitor bypasses the device at switching frequencies. Design equations:

C_snub = L_loop / Z_char^2, where Z_char = (L_loop / Coss)^0.5

For L_loop = 15 nH and Coss = 200 pF: Z_char = 274 ohms, C_snub = 200 pF. The resistor is set to Z_char / 2 = 137 ohms. In practice, values are swept experimentally to achieve critical damping while minimizing added losses.

11. Measurement Techniques

Accurate characterization of parasitic inductance requires appropriate measurement tools. Three methods are relevant:

Vector Network Analyzer (VNA) impedance measurement: The most accurate method for characterizing L, C, and R of individual components and small assemblies. A VNA sweeping 100 kHz to 100 MHz can characterize the complex impedance of a busbar, capacitor, or connector with high accuracy. Calibration at the measurement plane is essential.

Double-pulse test: A practical in-circuit method for evaluating total commutation loop inductance. The device is pulsed with a defined current; at turn-off, the voltage overshoot and ringing frequency both reveal the effective inductance: L_eff = Vpeak / (dI/dt) from the measured overshoot, or L_eff = 1 / (4pi^2 x f_ring^2 x Coss) from the ringing frequency.

High-bandwidth probing: Measuring fast switching transients requires probes with bandwidth above 500 MHz. A standard 10:1 passive probe at 100 MHz will heavily distort SiC switching waveforms and can underreport peak voltages by 30-50%. Differential high-voltage probes (1000V+) or isolated floating probes are required for safe measurement at high bus voltages.

12. Technology Comparison: Loop Inductance Targets

13. Worked Example: 800V, 300A Half-Bridge

Target: 800V DC bus, 300A peak current, 100 kHz switching, 1200V-rated SiC devices (absolute max Vds = 1200V). Available overshoot budget: 1200V - 800V - 100V margin = 300V. Target dI/dt = 15 A/ns.

• Required L_loop: V = L x dI/dt, so L_max = 300V / 15 A/ns = 20 nH
• Busbar design: Laminated copper busbar, 0.5 mm Kapton insulation, 80 mm wide conductors. Estimated inductance: 6 nH for 150 mm length.
• DC link capacitor: 4x 100 uF, 900V film capacitors with 5 nH ESL each. Paralleled ESL: 1.25 nH. Placed within 20 mm of device pads.
• Device package: Low-inductance SiC module, 6 nH internal. Total estimated loop: 6 + 1.25 + 6 + connector/trace ~2 nH = 15.25 nH. Within budget.
• Ringing frequency: Coss at 800V approximately 150 pF. f_ring = 1 / (2pi x sqrt(15 nH x 150 pF)) = 106 MHz. Ringing amplitude = sqrt(L/C) x I = 316 ohm x 0.3A residual = acceptable. Main concern is turn-off spike, not ringing.
• Peak voltage: 800V + 15 nH x 15 A/ns = 800 + 225 = 1025V. Margin to 1200V: 175V. Acceptable with measured validation.

14. References

• Wolfspeed Application Note: "Power Module Parasitic Inductance Extraction and Validation" (CRD-06DD12P)
• Rodriguez, M. et al., "Parasitic Inductance Reduction in High-Speed Power Converters," IEEE APEC, 2017
• Lemmon, A. et al., "Ultrahigh-Speed Gallium-Nitride-Based Power Inverter: Part II - Dynamic Characterization," IEEE Trans. Power Electronics, 2016
• Infineon Application Note: "Measurement of Parasitic Inductance with Impedance Analyzer" (AN 2018-05)
• IPC-2141A: Controlled Impedance Circuit Boards and High-Speed Logic Design
• Burkart, R. et al., "Comparative Evaluation of SiC and Si PV Inverter Systems Based on Power Density and Efficiency," IEEE COMPEL, 2013